(1) Field of the Invention
The present invention relates generally to methods of fabricating a gate dielectric and a mini-spacer, and more particularly, to methods of patterning gate structures with high-k gate dielectric films and mini-spacers in the fabrication of semiconductor devices and integrated circuits.
(2) Description of the Prior Art
The current generation ultra large-scale integrated (ULSI) circuits use predominantly field effect transistor (FET) devices, having poly-silicon gate electrode, silicon dioxide gate dielectric, and self-aligned source/drain regions. Typical process of fabricating an FET consists of growing a thin gate silicon dioxide on a silicon substrate and then forming the poly-silicon gate electrode. Source/drain (S/D) regions are then formed adjacent to the gate electrode, which then defines the FET gate length as the distance under the poly-silicon gate between the S/D regions. The gate length and the control of gate length is critical, particularly as channel lengths continue to decrease to achieve high device densities, since short channel effects (SCE) can occur in the device. SCE effects become predominant since band-gap and junction potentials cannot be scaled with channel length, being dependent on the substrate material (i.e. silicon).
Fabrication of the gate electrode structure is critical in achieving optimum performance of the MOSFFT (metal-oxide-silicon field effect transistor) device. The gate stack, consisting of the gate electrode and the gate dielectric, essentially determines the operating speed and reliability of the device.
Although silicon dioxide has been the dielectric of choice for many years because of ease of forming the film and patterning it, high-k refractory metal oxides are being increasingly experimented in recent years. The motivation is that high-k gate dielectric films reduce the equivalent gate oxide thickness between the gate metal and the substrate, thereby increasing device performance. If silicon dioxide has to be used in ULSI devices with short channel length, it needs to be quite thin to achieve large capacitance values and formation of nanometer range, high quality oxides without defects is quite difficult if not impossible. Several gate structures with high-k gate dielectric have been proposed in prior art. However, patterning of high-k films, unlike the conventional silicon oxides or nitrided oxides, is difficult for two main reasons: i) plasma etching of these films that do not easily form volatile reaction products requires high self-developed or applied bias voltages will cause device damage of the silicon surface of the transistor and ii) alternatively, non damaging wet etching processes result in poor dimensional control of the FET channel length and are prone to etch residues that are hard to remove during post-processing steps.
U.S. Pat. No. 5,447,874 describes a method of producing devices with improved gate length control, eliminating contamination induced surface damage, leakage problems without increasing processing steps. A gate opening is anisotropically etched in an oxide layer, creating a reverse gate metal image that has low gate length variability. Dual metal gate is then deposited and the excess gate metal is removed and the top surface of the gate planarized using chemical mechanical polishing. The remaining oxide is then removed. The patent refers to a dual metal gate with a conventional silicon dioxide gate dielectric film.
In U.S. Pat. No. 5,940,698, a device with a high performance gate structure and a fabrication process is described. According to the process disclosed, a gate insulating film is deposited over a substrate, a diffusion barrier layer is then formed over the gate-insulating layer, and a trench is etched in the diffusion barrier layer. In the trench, a metal gate electrode is formed. Although the high-k materials like cobalt niobate, barium strontium nitrate (BST), and tantalum oxide are proposed, the process described is quite complex and it is very likely that etch residues will be left on the silicon substrate when etching the high-k film within the gate trenches and around the gate structure, as previously discussed.
U.S. Pat. No. 5,960,270 describes a process of forming a metal-gate/metal-oxide/semiconductor MOS transistor with self-aligned source and drain electrodes formed before defining the metal gate. Although high-k metal oxides like TiO2 and Ta2O5 are mentioned as a part of a composite dielectric gate (e.g. grown oxide/deposited high-k material), no specific process is described or taught on how to pattern high-k films without the problems associated with post-etch residues.
U.S. Pat. No. 5,766,998 describes a method of forming reverse self-aligned FETs (field effect transistors) with gate electrode of sub-quarter micrometer dimensions that exceed the lithographic resolution limit with the use of polymer sidewall spacers. The process described includes forming a stack of titanium layer, and N+ doped first poly-silicon layer, and a silicon nitride layer over the device regions. Non-volatile polymer sidewall spacers are then formed on the sidewalls of the first openings. The sidewalls and the photo-resist together act as a mask for selectively etching the said stack down to the substrate and form the second opening to define the FET channel. A gate oxide is grown on the substrate in the channel opening. The gate dielectric film is a conventional silicon dioxide grown by thermal oxidation.
In U.S. Pat. No. 6,033,963, a method is described to form a metal gate for a CMOS device, using a replacement gate process. According to the process, a dummy gate oxide and a poly-silicon gate electrode layer are formed and patterned to forma a dummy gate. Lightly doped source and drain regions are formed using dummy gate as implant mask. After forming sidewall spacers, source and drain regions are formed and annealed. Tungsten layer is then selectively deposited on the exposed silicon surfaces. Blanket dielectric layer is then deposited and planarized, stopping on the tungsten layer. The tungsten overlying the dummy gate are removed, thereby forming a gate opening. A gate oxide layer and a metal gate electrode layer are then deposited in the gate opening and planarized, stopping on the blanket oxide layer. The structure uses a conventional oxide as the gate dielectric.